As shown in FIG. 1, a typical computer system (10) has, among other components, a microprocessor (12), one or more forms of memory (14), integrated circuits (16) having specific functionalities, and peripheral computer resources (not shown), e.g., monitor, keyboard, software programs, etc. These components communicate with one another via communication paths (19), e.g., wires, buses, etc., to accomplish the various tasks of the computer system (10).
In order to properly accomplish such tasks, the computer system (10) relies on the basis of time to coordinate its various operations. To that end, a crystal oscillator (18) generates a system clock signal (referred to and known in the art as a “reference clock signal” and shown in FIG. 1 as SYS13 CLK) to various parts of the computer system (10). Modern microprocessors and other integrated circuits, however, are typically capable of operating at frequencies significantly higher than the system clock signal, and thus, it becomes important to ensure that operations involving the microprocessor (12) and the other components of the computer system (10) use a proper and accurate reference of time.
One component used within the computer system (10) to ensure a proper reference of time among a system clock signal and a microprocessor clock signal, i.e., “chip clock signal,” is a type of clock signal generator known as a phase locked loop, or “PLL” (20). The PLL (20) is an electronic circuit that controls an oscillator such that the oscillator maintains a constant phase relative to a reference signal. Referring to FIG. 1, the PLL (20) has as its input the system clock signal, which is its reference signal, and outputs a chip clock signal (shown in FIG. 1 as CHIP_CLK) to the microprocessor (12). The system clock signal and chip clock signal have a specific phase and frequency relationship controlled by the PLL (20). This relationship between the phases and frequencies of the system clock signal and chip clock signal ensures that the various components within the microprocessor (12) use a controlled and accounted for reference of time. When this relationship is not maintained by the PLL (20), however, the operations within the computer system (10) become non-deterministic.
For example, the system clock signal may have a small voltage potential swing and a slow transition time from a low voltage potential to a high voltage potential, and vice versa, of the small voltage potential swing. The chip clock signal may have a voltage potential swing that is substantially the same as a difference between power supplies' voltage potentials. Also, a transition time from a low voltage potential to a high voltage potential, and vice versa, for the chip clock signal may be faster than the transition time for the system clock signal. The differences between the system clock signal and the chip clock signal may cause a difference in a propagation time through buffers used in the PLL (20). Accordingly, a static phase error may occur. Also, process variations, temperature variations, and/or voltage variations of the microprocessor (12) on which the PLL (20) resides may affect the operation of the PLL (20).
Furthermore, communications between devices, e.g., the microprocessor (12) and integrated circuits (16), require a controlled and accounted for reference of time. For example, FIG. 2 shows a typical communication system (100). A data signal is transmitted from circuit A (112) (i.e., transmitting circuit) to circuit B (134) (i.e., receiving circuit) on a data path (118). The data signal is generated by a logic circuit (114) and output by a driver circuit (116) on circuit A (112). The data signal on data path (118) is propagated to a receiver circuit (136) on circuit B (134). Depending on a process variations, temperature variations, and/or voltage variations of the receiver circuit (136), a time delay may vary between an arrival of the data signal on data path (118) and a corresponding signal representative of the data signal as a local data signal (142). In other words, a propagation delay through the receiver circuit (136) depends on the process variations, temperature variations, and/or voltage variations of an integrated circuit on which the receiving circuit (136) resides.
Although not shown, the communication system (100) could also have a path to transmit a data signal from circuit B (134) to circuit A (112). Accordingly, a propagation delay through a receiver circuit (not shown) on circuit A (112) may vary depending on process variations, temperature variations, and/or voltage variations.
Furthermore, process variations, temperature variations, and/or voltage variations may occur within a single integrated circuit. For example, circuit B (134) may include a plurality of receiver circuits (e.g., receiver circuit (136)) to receive data external and/or internal to circuit B (134). Each of the plurality of receiver circuits may have a propagation delay that differs from the other receiver circuits dependent on process variations, temperature variations, and/or voltage variations.